Initial Commit
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commit
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[target.thumbv7m-none-eabi]
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# uncomment this to make `cargo run` execute programs on QEMU
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# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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# uncomment ONE of these three option to make `cargo run` start a GDB session
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# which option to pick depends on your system
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# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
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# runner = "gdb-multiarch -q -x openocd.gdb"
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# runner = "gdb -q -x openocd.gdb"
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rustflags = [
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# LLD (shipped with the Rust toolchain) is used as the default linker
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"-C", "link-arg=-Tlink.x",
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# if you run into problems with LLD switch to the GNU linker by commenting out
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# this line
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# "-C", "linker=arm-none-eabi-ld",
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# if you need to link to pre-compiled C libraries provided by a C toolchain
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# use GCC as the linker by commenting out both lines above and then
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# uncommenting the three lines below
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# "-C", "linker=arm-none-eabi-gcc",
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# "-C", "link-arg=-Wl,-Tlink.x",
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# "-C", "link-arg=-nostartfiles",
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]
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[build]
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# Pick ONE of these compilation targets
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# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+
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target = "thumbv7m-none-eabi" # Cortex-M3
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# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
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# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
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target remote :3333
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monitor arm semihosting enable
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load
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tbreak main
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monitor reset halt
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continue
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#source .gdbdash
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**/*.rs.bk
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.#*
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.gdb_history
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Cargo.lock
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target/
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[package]
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authors = ["sebastian"]
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edition = "2018"
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readme = "README.md"
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name = "STM32F1Test"
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version = "0.1.0"
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[dependencies]
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cortex-m = "0.5.8"
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cortex-m-rt = "0.6.5"
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cortex-m-semihosting = "0.3.2"
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panic-halt = "0.2.0"
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[dependencies.stm32f1]
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version = "0.7.0"
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features = ["stm32f103"]
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# Uncomment for the panic example.
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# panic-itm = "0.4.0"
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# Uncomment for the allocator example.
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# alloc-cortex-m = "0.3.5"
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# Uncomment for the device example.
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# [dependencies.stm32f30x]
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# features = ["rt"]
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# version = "0.7.1"
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# this lets you use `cargo fix`!
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[[bin]]
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name = "STM32F1Test"
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test = false
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bench = false
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[profile.release]
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codegen-units = 1 # better optimizations
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debug = true # symbols are nice and they don't increase the size on Flash
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lto = true # better optimizations
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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// Put the linker script somewhere the linker can find it
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("memory.x"))
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.unwrap()
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.write_all(include_bytes!("memory.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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// Only re-run the build script when memory.x is changed,
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// instead of when any part of the source code changes.
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println!("cargo:rerun-if-changed=memory.x");
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}
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MEMORY
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{
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/* STM32f1*/
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FLASH : ORIGIN = 0x08000000, LENGTH = 0x00020000
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RAM : ORIGIN = 0x20000000, LENGTH = 0x00005000
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}
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/* This is where the call stack will be allocated. */
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/* The stack is of the full descending type. */
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/* You may want to use this variable to locate the call stack and static
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variables in different memory regions. Below is shown the default value */
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/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
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/* You can use this symbol to customize the location of the .text section */
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/* If omitted the .text section will be placed right after the .vector_table
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section */
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/* This is required only on microcontrollers that store some configuration right
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after the vector table */
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/* _stext = ORIGIN(FLASH) + 0x400; */
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/* Example of putting non-initialized variables into custom RAM locations. */
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/* This assumes you have defined a region RAM2 above, and in the Rust
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sources added the attribute `#[link_section = ".ram2bss"]` to the data
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you want to place there. */
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/* Note that the section will not be zero-initialized by the runtime! */
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/* SECTIONS {
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.ram2bss (NOLOAD) : ALIGN(4) {
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*(.ram2bss);
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. = ALIGN(4);
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} > RAM2
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} INSERT AFTER .bss;
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*/
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#!/bin/bash
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cargo build || exit -1
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arm-none-eabi-gdb target/thumbv7m-none-eabi/debug/STM32F1Test
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#![no_std]
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#![no_main]
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// pick a panicking behavior
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extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
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// extern crate panic_abort; // requires nightly
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// extern crate panic_itm; // logs messages over ITM; requires ITM support
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use cortex_m_semihosting::hprintln; // logs messages to the host; requires a debugger
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use cortex_m::asm;
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use cortex_m_rt::entry;
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use stm32f1::stm32f103;
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#[entry]
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fn main() -> ! {
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hprintln!("Hello, world!").unwrap();
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let peripherals = stm32f103::Peripherals::take().unwrap();
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let gpioc = &peripherals.GPIOC;
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let rcc = &peripherals.RCC;
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let flash = &peripherals.FLASH;
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flash.acr.write(|w| unsafe { w.latency().bits(1)});
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rcc.cr.write(|w| w.hseon().set_bit());
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while rcc.cr.read().hserdy().is_not_ready() {};
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hprintln!("HSE Ready.").unwrap();
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rcc.cfgr.write(|w| {
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w.pllmul().mul12()
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.pllsrc().hse_div_prediv()
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.pllxtpre().div2()
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.ppre2().div2()
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});
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rcc.cr.modify(|_, w| w.pllon().on());
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while rcc.cr.read().pllrdy().is_not_ready() {};
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rcc.cfgr.modify(|_, w| { w.sw().pll() });
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hprintln!("PLL running.").unwrap();
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// enable the GPIO clock for IO port C
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rcc.apb2enr.write(|w| w.iopcen().set_bit());
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gpioc.crh.write(|w| {
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w.mode13().bits(3)
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.cnf13().bits(0b00)
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});
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loop{
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gpioc.bsrr.write(|w| w.bs13().set_bit());
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cortex_m::asm::delay(500_000);
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gpioc.brr.write(|w| w.br13().set_bit());
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cortex_m::asm::delay(500_000);
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//hprintln!("Blink").unwrap();
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}
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}
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