62 lines
1.6 KiB
Rust
62 lines
1.6 KiB
Rust
#![no_std]
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#![no_main]
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// pick a panicking behavior
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extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
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// extern crate panic_abort; // requires nightly
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// extern crate panic_itm; // logs messages over ITM; requires ITM support
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use cortex_m_semihosting::hprintln; // logs messages to the host; requires a debugger
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use cortex_m::asm;
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use cortex_m_rt::entry;
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use stm32f1::stm32f103;
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#[entry]
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fn main() -> ! {
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hprintln!("Hello, world!").unwrap();
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let peripherals = stm32f103::Peripherals::take().unwrap();
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let gpioc = &peripherals.GPIOC;
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let rcc = &peripherals.RCC;
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let flash = &peripherals.FLASH;
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flash.acr.write(|w| unsafe { w.latency().bits(1)});
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rcc.cr.write(|w| w.hseon().set_bit());
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while rcc.cr.read().hserdy().is_not_ready() {};
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hprintln!("HSE Ready.").unwrap();
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rcc.cfgr.write(|w| {
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w.pllmul().mul12()
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.pllsrc().hse_div_prediv()
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.pllxtpre().div2()
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.ppre2().div2()
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});
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rcc.cr.modify(|_, w| w.pllon().on());
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while rcc.cr.read().pllrdy().is_not_ready() {};
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rcc.cfgr.modify(|_, w| { w.sw().pll() });
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hprintln!("PLL running.").unwrap();
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// enable the GPIO clock for IO port C
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rcc.apb2enr.write(|w| w.iopcen().set_bit());
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gpioc.crh.write(|w| {
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w.mode13().bits(3)
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.cnf13().bits(0b00)
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});
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loop{
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gpioc.bsrr.write(|w| w.bs13().set_bit());
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cortex_m::asm::delay(500_000);
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gpioc.brr.write(|w| w.br13().set_bit());
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cortex_m::asm::delay(500_000);
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//hprintln!("Blink").unwrap();
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}
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}
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