#![no_std]
#![no_main]

// pick a panicking behavior
extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
// extern crate panic_abort; // requires nightly
// extern crate panic_itm; // logs messages over ITM; requires ITM support
use cortex_m_semihosting::hprintln; // logs messages to the host; requires a debugger

use cortex_m::asm;
use cortex_m_rt::entry;
use stm32f1::stm32f103;

#[entry]
fn main() -> ! {
    hprintln!("Hello, world!").unwrap();

    let peripherals = stm32f103::Peripherals::take().unwrap();

    let gpioc = &peripherals.GPIOC;
    let rcc = &peripherals.RCC;
    let flash = &peripherals.FLASH;

    flash.acr.write(|w| unsafe { w.latency().bits(1)});

    rcc.cr.write(|w| w.hseon().set_bit());
    while rcc.cr.read().hserdy().is_not_ready() {};

    hprintln!("HSE Ready.").unwrap();

    rcc.cfgr.write(|w| {
        w.pllmul().mul12()
        .pllsrc().hse_div_prediv()
        .pllxtpre().div2()
        .ppre2().div2()
    });

    rcc.cr.modify(|_, w| w.pllon().on());
    while rcc.cr.read().pllrdy().is_not_ready() {};

    rcc.cfgr.modify(|_, w| { w.sw().pll() });


    hprintln!("PLL running.").unwrap();


    // enable the GPIO clock for IO port C
    rcc.apb2enr.write(|w| w.iopcen().set_bit());
    gpioc.crh.write(|w| {
        w.mode13().bits(3)
        .cnf13().bits(0b00)
    });

    loop{
        gpioc.bsrr.write(|w| w.bs13().set_bit());
        cortex_m::asm::delay(500_000);
        gpioc.brr.write(|w| w.br13().set_bit());
        cortex_m::asm::delay(500_000);
        //hprintln!("Blink").unwrap();
    }
}