Initial commit
This commit is contained in:
commit
507bd0dfef
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[target.'cfg(all(target_arch = "arm", target_os = "none"))']
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# TODO(2) replace `$CHIP` with your chip's name (see `probe-run --list-chips` output)
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runner = "probe-run --chip STM32F103C8"
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rustflags = [
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"-C", "linker=flip-link",
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"-C", "link-arg=-Tlink.x",
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"-C", "link-arg=-Tdefmt.x",
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# This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x
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# See https://github.com/rust-embedded/cortex-m-quickstart/pull/95
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"-C", "link-arg=--nmagic",
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]
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[build]
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target = "thumbv7m-none-eabi" # Cortex-M3
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[alias]
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rb = "run --bin"
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rrb = "run --release --bin"
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/target
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Cargo.lock
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[package]
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authors = ["LongHairedHacker <sebastian@sebastians-site.de>"]
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name = "wspr-beacon"
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edition = "2018"
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version = "0.1.0"
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[dependencies]
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cortex-m = "0.7.6"
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cortex-m-rt = "0.7.2"
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cortex-m-rtic = "1.1.3"
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defmt = "0.3.2"
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defmt-rtt = "0.3.2"
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panic-probe = { version = "0.3.0", features = ["print-defmt"] }
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stm32f1xx-hal = { version = "0.9.0", features = ["stm32f103", "rt"] }
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embedded-hal = {version = "0.2.3"}
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nb = "1.0.0"
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arrayvec = {version = "0.7.0", default-features = false}
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systick-monotonic = "1.0.0"
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[features]
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# set logging levels here
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default = [
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"defmt-default",
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# "dependency-a/defmt-trace",
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]
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# do NOT modify these features
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defmt-default = []
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defmt-trace = []
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defmt-debug = []
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defmt-info = []
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defmt-warn = []
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defmt-error = []
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# cargo build/run
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[profile.dev]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 'z' # <-
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overflow-checks = true # <-
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# cargo test
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[profile.test]
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codegen-units = 1
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debug = 2
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debug-assertions = true # <-
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incremental = false
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opt-level = 3 # <-
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overflow-checks = true # <-
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# cargo build/run --release
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[profile.release]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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# cargo test --release
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[profile.bench]
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codegen-units = 1
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debug = 2
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debug-assertions = false # <-
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incremental = false
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lto = 'fat'
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opt-level = 3 # <-
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overflow-checks = false # <-
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# uncomment this to switch from the crates.io version of defmt to its git version
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# check app-template's README for instructions
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# [patch.crates-io]
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# defmt = { git = "https://github.com/knurling-rs/defmt", rev = "use defmt version reported by `probe-run --version`" }
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# defmt-rtt = { git = "https://github.com/knurling-rs/defmt", rev = "use defmt version reported by `probe-run --version`" }
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# defmt-test = { git = "https://github.com/knurling-rs/defmt", rev = "use defmt version reported by `probe-run --version`" }
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# panic-probe = { git = "https://github.com/knurling-rs/defmt", rev = "use defmt version reported by `probe-run --version`" }
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/* Fake bluepill using STM32F103C8T6 */
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MEMORY
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{
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FLASH : ORIGIN = 0x08000000, LENGTH = 64K
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RAM : ORIGIN = 0x20000000, LENGTH = 20K
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}
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#![no_main]
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#![no_std]
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use defmt_rtt as _; // global logger
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use panic_probe as _;
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use stm32f1xx_hal as _;
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// same panicking *behavior* as `panic-probe` but doesn't print a panic message
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// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
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#[defmt::panic_handler]
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fn panic() -> ! {
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cortex_m::asm::udf()
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}
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use rtic::app;
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mod si5153;
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#[app(device = stm32f1xx_hal::pac, peripherals = true, dispatchers = [TIM2])]
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mod app {
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use core::num::dec2flt::float;
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use stm32f1xx_hal::{
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adc,
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gpio::{
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self, gpioa, gpiob, gpioc, Alternate, Analog, Floating, Input, OpenDrain, Output,
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PushPull, CRL,
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},
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i2c,
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i2c::BlockingI2c,
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pac::{ADC1, I2C1},
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prelude::*,
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serial::{self, Config, Serial},
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stm32,
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timer::{self, Event},
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};
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use systick_monotonic::Systick;
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use arrayvec::ArrayString;
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use crate::si5153;
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type AppI2C1 = BlockingI2c<
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I2C1,
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(
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gpiob::PB6<Alternate<OpenDrain>>,
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gpiob::PB7<Alternate<OpenDrain>>,
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),
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>;
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#[monotonic(binds = SysTick, default = true)]
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type MonoTimer = Systick<1_000_000>;
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#[shared]
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struct Shared {}
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#[local]
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struct Local {
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pll: si5153::Si5153<AppI2C1>,
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i2c: AppI2C1,
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board_led: gpioc::PC13<Output<PushPull>>,
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adc1: adc::Adc<ADC1>,
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mic_in: gpio::Pin<Analog, CRL, 'A', 4>,
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}
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#[init]
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fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) {
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let mut flash = cx.device.FLASH.constrain();
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let rcc = cx.device.RCC.constrain();
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// Freeze the configuration of all the clocks in the system and store the frozen frequencies in
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// `clocks`
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let clocks = rcc
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.cfgr
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.use_hse(8.MHz())
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.sysclk(72.MHz())
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.pclk1(36.MHz())
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.freeze(&mut flash.acr);
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defmt::info!("Clock Setup done");
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let mono = Systick::new(cx.core.SYST, clocks.sysclk().to_Hz());
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let mut afio = cx.device.AFIO.constrain();
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// Acquire the GPIOC peripheral
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let mut gpioa = cx.device.GPIOA.split();
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let mut gpiob = cx.device.GPIOB.split();
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let mut gpioc = cx.device.GPIOC.split();
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let board_led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
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let scl = gpiob.pb6.into_alternate_open_drain(&mut gpiob.crl);
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let sda = gpiob.pb7.into_alternate_open_drain(&mut gpiob.crl);
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let mut i2c = i2c::BlockingI2c::i2c1(
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cx.device.I2C1,
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(scl, sda),
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&mut afio.mapr,
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i2c::Mode::Standard {
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frequency: 400.kHz(),
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},
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clocks,
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5,
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1,
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5,
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5,
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);
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let mut pll = si5153::Si5153::new(&i2c);
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pll.init(&mut i2c, 25000000, 800000000, 800000000);
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pll.set_ms_source(&mut i2c, si5153::Multisynth::MS0, si5153::PLL::A);
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let adc1 = adc::Adc::adc1(cx.device.ADC1, clocks);
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let mic_in = gpioa.pa4.into_analog(&mut gpioa.crl);
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let mut pwm =
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cx.device
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.TIM2
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.pwm_hz::<Tim3NoRemap, _, _>(pins, &mut afio.mapr, 4800.Hz(), &clocks);
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transmit::spawn().unwrap();
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(
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Shared {},
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Local {
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i2c,
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pll,
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board_led,
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adc1,
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mic_in,
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},
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init::Monotonics(mono),
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)
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}
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#[task(local=[pll, i2c, adc1, mic_in])]
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fn transmit(mut ctx: transmit::Context) {
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let mut adc = ctx.local.adc1;
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let mut mic_in = ctx.local.mic_in;
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let data: u16 = adc.read(&mut *mic_in).unwrap();
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let sample = (data as f32 / u16::MAX as f32);
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transmit::spawn_after(208.micros().into()).unwrap();
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}
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}
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@ -0,0 +1,175 @@
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use core::marker::PhantomData;
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use embedded_hal::blocking::i2c;
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const I2C_ADDR: u8 = 96;
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const CLK_ENABLE_CONTROL: u8 = 3;
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//const PLLX_SRC: u8 = 15;
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const PLL_RESET: u8 = 177;
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const XTAL_LOAD_CAP: u8 = 183;
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#[derive(PartialEq, Copy, Clone)]
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pub enum PLL {
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A,
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B,
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}
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const PLL_BASE_ADDR: [u8; 2] = [26, 34];
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impl PLL {
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fn base_address(&self) -> u8 {
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return PLL_BASE_ADDR[*self as usize];
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}
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}
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#[derive(Copy, Clone)]
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pub enum Multisynth {
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MS0,
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MS1,
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MS2,
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}
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const MS_BASE_ADDR: [u8; 3] = [42, 50, 58];
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const MS_CTRL_ADDR: [u8; 3] = [16, 17, 18];
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impl Multisynth {
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fn base_address(&self) -> u8 {
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return MS_BASE_ADDR[*self as usize];
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}
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fn ctrl_address(&self) -> u8 {
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return MS_CTRL_ADDR[*self as usize];
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}
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}
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pub struct PllParams {
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pub p1: u32,
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pub p2: u32,
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pub p3: u32,
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}
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pub struct Si5153<I2C> {
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// Marker that makes sure we always get the same I2C
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i2c: PhantomData<I2C>,
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pll_freqs: [u32; 2],
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outputs: u8,
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ms_srcs: [PLL; 3],
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}
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impl<I2C, E> Si5153<I2C>
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where
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I2C: i2c::Write<Error = E>,
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{
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pub fn new(_i2c: &I2C) -> Self {
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Si5153 {
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i2c: PhantomData,
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pll_freqs: [0, 0],
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outputs: 0,
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ms_srcs: [PLL::A, PLL::A, PLL::A],
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}
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}
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pub fn init(&mut self, i2c: &mut I2C, freq_xtal: u32, freq_a: u32, freq_b: u32) {
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self.pll_freqs[PLL::A as usize] = freq_a;
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self.pll_freqs[PLL::B as usize] = freq_b;
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self.outputs = 0xFF;
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs); // Disable all outputs
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self.write_byte_reg(i2c, XTAL_LOAD_CAP, 0xD2); //crystal load capacitor = 10pF
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self.write_byte_reg(i2c, PLL_RESET, 0xA0); // Reset both PLLs
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for ms in [Multisynth::MS0, Multisynth::MS1, Multisynth::MS2].iter() {
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self.ms_srcs[*ms as usize] = PLL::A;
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self.write_byte_reg(i2c, ms.ctrl_address(), 0x0F); // MSi as Source, PLLA to MSi, 8 mA output
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}
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for pll in [PLL::A, PLL::B].iter() {
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let fdiv = self.pll_freqs[*pll as usize] / freq_xtal;
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let rm = self.pll_freqs[*pll as usize] % freq_xtal;
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//TODO: Find better way to determine c and b
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let c = 0x0FFFFF;
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let a = fdiv;
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let b = ((rm as u64) * (c as u64) / (freq_xtal as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, pll.base_address(), ¶ms)
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}
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}
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pub fn enable_ms_output(&mut self, i2c: &mut I2C, synth: Multisynth) {
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self.outputs &= !(1 << (synth as u8));
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs);
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}
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pub fn disable_ms_output(&mut self, i2c: &mut I2C, synth: Multisynth) {
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self.outputs |= 1 << (synth as u8);
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs);
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}
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pub fn set_ms_source(&mut self, i2c: &mut I2C, synth: Multisynth, pll: PLL) {
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let value: u8 = if pll == PLL::A {
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self.ms_srcs[synth as usize] = PLL::A;
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0x0F // MS as Source, PLLA to MS, 8 mA output
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} else {
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self.ms_srcs[synth as usize] = PLL::B;
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0x2F // MS as Source, PLLB to MS, 8 mA output
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};
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self.write_byte_reg(i2c, synth.ctrl_address(), value);
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}
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pub fn set_ms_freq(&mut self, i2c: &mut I2C, synth: Multisynth, freq: u32) {
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let pll = self.ms_srcs[synth as usize];
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let fdiv = self.pll_freqs[pll as usize] / freq;
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let rm = self.pll_freqs[pll as usize] % freq;
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//TODO: Find better way to determine c and b
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let c: u32 = 0x0FFFFF;
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let a: u32 = fdiv;
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let b: u32 = ((rm as u64) * (c as u64) / (freq as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, synth.base_address(), ¶ms)
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}
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fn write_byte_reg(&self, i2c: &mut I2C, reg_addr: u8, data: u8) {
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let res = i2c.write(I2C_ADDR, &[reg_addr, data]);
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if res.is_err() {
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panic!("i2c write failed. regAdder: {}", reg_addr)
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}
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}
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fn write_params(&self, i2c: &mut I2C, base: u8, params: &PllParams) {
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let data: [u8; 9] = [
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base,
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((params.p3 & 0x00FF00) >> 8) as u8,
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(params.p3 & 0x0000FF) as u8,
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((params.p1 & 0x030000) >> 16) as u8,
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((params.p1 & 0x00FF00) >> 8) as u8,
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(params.p1 & 0x0000FF) as u8,
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(((params.p3 & 0x0F0000) >> 12) | ((params.p2 & 0x0F0000) >> 16)) as u8,
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((params.p2 & 0x00FF00) >> 8) as u8,
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(params.p2 & 0x0000FF) as u8,
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];
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let res = i2c.write(I2C_ADDR, &data);
|
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if res.is_err() {
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panic!("i2c write failed. regAdder: {}", base)
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}
|
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}
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|
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pub fn write_synth_params(&self, i2c: &mut I2C, synth: Multisynth, params: &PllParams) {
|
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self.write_params(i2c, synth.base_address(), params);
|
||||
}
|
||||
}
|
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