Added PLL reset to phase setting code
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@ -152,6 +152,15 @@ where
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pub fn set_ms_phase(&mut self, i2c: &mut I2C, synth: Multisynth, phase: u8) {
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self.write_byte_reg(i2c, synth.phoff_address(), phase);
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match self.ms_srcs[synth as usize] {
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PLL::A => {
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self.write_byte_reg(i2c, PLL_RESET, 1 << 5);
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}
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PLL::B => {
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self.write_byte_reg(i2c, PLL_RESET, 1 << 7);
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}
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}
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}
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pub fn pll_reset(&mut self, i2c: &mut I2C) {
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