152 lines
4.9 KiB
C
152 lines
4.9 KiB
C
#include <avr/pgmspace.h>
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#include "ov7670.h"
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// Initialiezer Lists borrowed from https://github.com/dasaki/arduvision
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const struct ov7670_register yuv422_ov7670[] PROGMEM = {
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{ REG_COM7, 0x0 }, /* Selects YUV mode */
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{ REG_RGB444, 0 }, /* No RGB444 please */
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{ REG_COM1, 0 },
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{ REG_COM15, COM15_R00FF },
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{ REG_COM9, 0x6A }, /* 128x gain ceiling; 0x8 is reserved bit */
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{ 0x4f, 0x80 }, /* "matrix coefficient 1" */
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{ 0x50, 0x80 }, /* "matrix coefficient 2" */
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{ 0x51, 0 }, /* vb */
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{ 0x52, 0x22 }, /* "matrix coefficient 4" */
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{ 0x53, 0x5e }, /* "matrix coefficient 5" */
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{ 0x54, 0x80 }, /* "matrix coefficient 6" */
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{ REG_COM13, COM13_UVSAT },
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{ 0xff, 0xff }, /* END MARKER */
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};
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//from the linux driver
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const struct ov7670_register ov7670_default_regs[] PROGMEM = {
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{ REG_COM7, COM7_RESET },
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{ REG_TSLB, 0x04 }, /* OV */
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{ REG_COM7, 0 }, /* VGA */
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/*
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* Set the hardware window. These values from OV don't entirely
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* make sense - hstop is less than hstart. But they work...
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*/
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{ REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
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{ REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
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{ REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
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{ REG_COM3, 0 }, { REG_COM14, 0 },
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/* Mystery scaling numbers */
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{ 0x70, 0x3a }, { 0x71, 0x35 },
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{ 0x72, 0x11 }, { 0x73, 0xf0 },
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{ 0xa2,/* 0x02 changed to 1*/1 }, { REG_COM10, 0x0 },
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/* Gamma curve values */
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{ 0x7a, 0x20 }, { 0x7b, 0x10 },
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{ 0x7c, 0x1e }, { 0x7d, 0x35 },
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{ 0x7e, 0x5a }, { 0x7f, 0x69 },
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{ 0x80, 0x76 }, { 0x81, 0x80 },
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{ 0x82, 0x88 }, { 0x83, 0x8f },
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{ 0x84, 0x96 }, { 0x85, 0xa3 },
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{ 0x86, 0xaf }, { 0x87, 0xc4 },
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{ 0x88, 0xd7 }, { 0x89, 0xe8 },
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/* AGC and AEC parameters. Note we start by disabling those features,
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then turn them only after tweaking the values. */
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{ REG_COM8, COM8_FASTAEC | COM8_AECSTEP },
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{ REG_GAIN, 0 }, { REG_AECH, 0 },
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{ REG_COM4, 0x40 }, /* magic reserved bit */
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{ REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
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{ REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
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{ REG_AEW, 0x95 }, { REG_AEB, 0x33 },
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{ REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
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{ REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
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{ REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
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{ REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
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{ REG_HAECC7, 0x94 },
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{ REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC },
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{ 0x30, 0 }, { 0x31, 0 },//disable some delays
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/* Almost all of these are magic "reserved" values. */
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{ REG_COM5, 0x61 }, { REG_COM6, 0x4b },
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{ 0x16, 0x02 }, { REG_MVFP, 0x07 },
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{ 0x21, 0x02 }, { 0x22, 0x91 },
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{ 0x29, 0x07 }, { 0x33, 0x0b },
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{ 0x35, 0x0b }, { 0x37, 0x1d },
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{ 0x38, 0x71 }, { 0x39, 0x2a },
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{ REG_COM12, 0x78 }, { 0x4d, 0x40 },
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{ 0x4e, 0x20 }, { REG_GFIX, 0 },
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/*{0x6b, 0x4a},*/{ 0x74, 0x10 },
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{ 0x8d, 0x4f }, { 0x8e, 0 },
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{ 0x8f, 0 }, { 0x90, 0 },
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{ 0x91, 0 }, { 0x96, 0 },
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{ 0x9a, 0 }, { 0xb0, 0x84 },
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{ 0xb1, 0x0c }, { 0xb2, 0x0e },
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{ 0xb3, 0x82 }, { 0xb8, 0x0a },
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/* More reserved magic, some of which tweaks white balance */
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{ 0x43, 0x0a }, { 0x44, 0xf0 },
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{ 0x45, 0x34 }, { 0x46, 0x58 },
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{ 0x47, 0x28 }, { 0x48, 0x3a },
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{ 0x59, 0x88 }, { 0x5a, 0x88 },
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{ 0x5b, 0x44 }, { 0x5c, 0x67 },
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{ 0x5d, 0x49 }, { 0x5e, 0x0e },
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{ 0x6c, 0x0a }, { 0x6d, 0x55 },
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{ 0x6e, 0x11 }, { 0x6f, 0x9e }, /* it was 0x9F "9e for advance AWB" */
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{ 0x6a, 0x40 }, { REG_BLUE, 0x40 },
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{ REG_RED, 0x60 },
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{ REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_AGC | COM8_AEC | COM8_AWB },
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/* Matrix coefficients */
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{ 0x4f, 0x80 }, { 0x50, 0x80 },
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{ 0x51, 0 }, { 0x52, 0x22 },
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{ 0x53, 0x5e }, { 0x54, 0x80 },
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{ 0x58, 0x9e },
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{ REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
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{ 0x75, 0x05 }, { REG_REG76, 0xe1 },
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{ 0x4c, 0 }, { 0x77, 0x01 },
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{ REG_COM13, /*0xc3*/0x48 }, { 0x4b, 0x09 },
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{ 0xc9, 0x60 }, /*{REG_COM16, 0x38},*/
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{ 0x56, 0x40 },
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{ 0x34, 0x11 }, { REG_COM11, COM11_EXP | COM11_HZAUTO },
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{ 0xa4, 0x82/*Was 0x88*/ }, { 0x96, 0 },
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{ 0x97, 0x30 }, { 0x98, 0x20 },
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{ 0x99, 0x30 }, { 0x9a, 0x84 },
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{ 0x9b, 0x29 }, { 0x9c, 0x03 },
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{ 0x9d, 0x4c }, { 0x9e, 0x3f },
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{ 0x78, 0x04 },
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/* Extra-weird stuff. Some sort of multiplexor register */
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{ 0x79, 0x01 }, { 0xc8, 0xf0 },
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{ 0x79, 0x0f }, { 0xc8, 0x00 },
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{ 0x79, 0x10 }, { 0xc8, 0x7e },
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{ 0x79, 0x0a }, { 0xc8, 0x80 },
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{ 0x79, 0x0b }, { 0xc8, 0x01 },
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{ 0x79, 0x0c }, { 0xc8, 0x0f },
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{ 0x79, 0x0d }, { 0xc8, 0x20 },
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{ 0x79, 0x09 }, { 0xc8, 0x80 },
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{ 0x79, 0x02 }, { 0xc8, 0xc0 },
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{ 0x79, 0x03 }, { 0xc8, 0x40 },
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{ 0x79, 0x05 }, { 0xc8, 0x30 },
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{ 0x79, 0x26 },
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{ 0xff, 0xff }, /* END MARKER */
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};
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void ov7670_init(void) {
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// WRST, RRST, WE
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DDRC |= (1 << PC3) | (1 << PC2) | (1 << PC1);
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// VSYNC
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DDRC &= ~(1 << PC0);
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// RCK
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DDRB |= (1 << PB5);
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// RST
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DDRD |= (1 << PD3);
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// Lower nibble of 8bit data, input
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DDRB &= ~0x0F;
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// Upper nibble of 8bit data, input
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DDRD &= ~0xF0;
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// Reset should be high
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ov7670_set_rst();
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// Write enable should be high
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ov7670_set_we();
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}
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