221 lines
10 KiB
C
221 lines
10 KiB
C
#ifndef __ov7670_H__
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#define __ov7670_H__ __ov7670_H__
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#include <stdint.h>
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#include <avr/io.h>
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#include <util/delay.h>
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#include "twi.h"
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static const uint8_t OV7670_ADDRESS = 0x42;
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void ov7670_init(void);
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struct ov7670_register {
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uint8_t reg_num;
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uint8_t value;
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};
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static inline uint8_t ov7670_write8(uint8_t reg, uint8_t value) {
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uint8_t data[2] = {reg, value};
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return twi_write(OV7670_ADDRESS, data, 2);
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}
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static inline uint8_t ov7670_vsync(void) { return (PINC & (1 << PC0)) != 0; }
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static inline void ov7670_wait_vsync(void) {
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while (ov7670_vsync())
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; // Wait until low
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while (!ov7670_vsync())
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; // Wait until high
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}
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static inline void ov7670_set_rst(void) { PORTD |= (1 << PD3); }
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static inline void ov7670_unset_rst(void) { PORTD &= ~(1 << PD3); }
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static inline void ov7670_set_wrst(void) { PORTC |= (1 << PC3); }
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static inline void ov7670_unset_wrst(void) { PORTC &= ~(1 << PC3); }
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static inline void ov7670_toggle_wrst(void) {
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ov7670_set_wrst();
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_delay_us(5);
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ov7670_unset_wrst();
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}
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static inline void ov7670_set_rrst(void) { PORTC |= (1 << PC2); }
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static inline void ov7670_unset_rrst(void) { PORTC &= ~(1 << PC2); }
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static inline void ov7670_toggle_rrst(void) {
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ov7670_set_rrst();
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_delay_us(5);
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ov7670_unset_rrst();
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}
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static inline void ov7670_set_we(void) { PORTC |= (1 << PC1); }
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static inline void ov7670_unset_we(void) { PORTC &= ~(1 << PC1); }
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static inline void ov7670_set_rck(void) { PORTB |= (1 << PB5); }
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static inline void ov7670_unset_rck(void) { PORTB &= ~(1 << PB5); }
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static inline void ov7670_toggle_rck(void) {
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ov7670_set_rck();
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_delay_us(5);
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ov7670_unset_rck();
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}
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static inline uint8_t ov7670_read_bits(void) {
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return (PINB & 0x0F) | (PIND & 0xF0);
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}
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// Register List borrowed from https://github.com/dasaki/arduvision
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/* Registers */
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static const uint8_t REG_GAIN = 0x00; /* Gain lower 8 bits (rest in vref) */
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static const uint8_t REG_BLUE = 0x01; /* blue gain */
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static const uint8_t REG_RED = 0x02; /* red gain */
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static const uint8_t REG_VREF = 0x03; /* Pieces of GAIN, VSTART, VSTOP */
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static const uint8_t REG_COM1 = 0x04; /* Control 1 */
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static const uint8_t COM1_CCIR656 = 0x40; /* CCIR656 enable */
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static const uint8_t REG_BAVE = 0x05; /* U/B Average level */
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static const uint8_t REG_GbAVE = 0x06; /* Y/Gb Average level */
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static const uint8_t REG_AECHH = 0x07; /* AEC MS 5 bits */
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static const uint8_t REG_RAVE = 0x08; /* V/R Average level */
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static const uint8_t REG_COM2 = 0x09; /* Control 2 */
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static const uint8_t COM2_SSLEEP = 0x10; /* Soft sleep mode */
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static const uint8_t REG_PID = 0x0a; /* Product ID MSB */
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static const uint8_t REG_VER = 0x0b; /* Product ID LSB */
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static const uint8_t REG_COM3 = 0x0c; /* Control 3 */
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static const uint8_t COM3_SWAP = 0x40; /* Byte swap */
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static const uint8_t COM3_SCALEEN = 0x08; /* Enable scaling */
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static const uint8_t COM3_DCWEN = 0x04; /* Enable downsamp/crop/window */
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static const uint8_t REG_COM4 = 0x0d; /* Control 4 */
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static const uint8_t REG_COM5 = 0x0e; /* All "reserved" */
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static const uint8_t REG_COM6 = 0x0f; /* Control 6 */
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static const uint8_t REG_AECH = 0x10; /* More bits of AEC value */
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static const uint8_t REG_CLKRC = 0x11; /* Clocl control */
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static const uint8_t CLK_EXT = 0x40; /* Use external clock directly */
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static const uint8_t CLK_SCALE = 0x3f; /* Mask for internal clock scale */
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static const uint8_t REG_COM7 = 0x12; /* Control 7 */ // REG mean address.
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static const uint8_t COM7_RESET = 0x80; /* Register reset */
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static const uint8_t COM7_FMT_MASK = 0x38;
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static const uint8_t COM7_FMT_VGA = 0x00;
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static const uint8_t COM7_FMT_CIF = 0x20; /* CIF format */
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static const uint8_t COM7_FMT_QVGA = 0x10; /* QVGA format */
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static const uint8_t COM7_FMT_QCIF = 0x08; /* QCIF format */
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static const uint8_t COM7_RGB = 0x04; /* bits 0 and 2 - RGB format */
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static const uint8_t COM7_YUV = 0x00; /* YUV */
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static const uint8_t COM7_BAYER = 0x01; /* Bayer format */
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static const uint8_t COM7_PBAYER = 0x05; /* "Processed bayer" */
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static const uint8_t REG_COM8 = 0x13; /* Control 8 */
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static const uint8_t COM8_FASTAEC = 0x80; /* Enable fast AGC/AEC */
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static const uint8_t COM8_AECSTEP = 0x40; /* Unlimited AEC step size */
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static const uint8_t COM8_BFILT = 0x20; /* Band filter enable */
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static const uint8_t COM8_AGC = 0x04; /* Auto gain enable */
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static const uint8_t COM8_AWB = 0x02; /* White balance enable */
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static const uint8_t COM8_AEC = 0x01; /* Auto exposure enable */
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static const uint8_t REG_COM9 = 0x14; /* Control 9- gain ceiling */
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static const uint8_t REG_COM10 = 0x15; /* Control 10 */
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static const uint8_t COM10_HSYNC = 0x40; /* HSYNC instead of HREF */
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static const uint8_t COM10_PCLK_HB = 0x20; /* Suppress PCLK on horiz blank */
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static const uint8_t COM10_HREF_REV = 0x08; /* Reverse HREF */
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static const uint8_t COM10_VS_LEAD = 0x04; /* VSYNC on clock leading edge */
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static const uint8_t COM10_VS_NEG = 0x02; /* VSYNC negative */
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static const uint8_t COM10_HS_NEG = 0x01; /* HSYNC negative */
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static const uint8_t REG_HSTART = 0x17; /* Horiz start high bits */
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static const uint8_t REG_HSTOP = 0x18; /* Horiz stop high bits */
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static const uint8_t REG_VSTART = 0x19; /* Vert start high bits */
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static const uint8_t REG_VSTOP = 0x1a; /* Vert stop high bits */
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static const uint8_t REG_PSHFT = 0x1b; /* Pixel delay after HREF */
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static const uint8_t REG_MIDH = 0x1c; /* Manuf. ID high */
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static const uint8_t REG_MIDL = 0x1d; /* Manuf. ID low */
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static const uint8_t REG_MVFP = 0x1e; /* Mirror / vflip */
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static const uint8_t MVFP_MIRROR = 0x20; /* Mirror image */
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static const uint8_t MVFP_FLIP = 0x10; /* Vertical flip */
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static const uint8_t REG_AEW = 0x24; /* AGC upper limit */
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static const uint8_t REG_AEB = 0x25; /* AGC lower limit */
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static const uint8_t REG_VPT = 0x26; /* AGC/AEC fast mode op region */
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static const uint8_t REG_HSYST = 0x30; /* HSYNC rising edge delay */
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static const uint8_t REG_HSYEN = 0x31; /* HSYNC falling edge delay */
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static const uint8_t REG_HREF = 0x32; /* HREF pieces */
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static const uint8_t REG_TSLB = 0x3a; /* lots of stuff */
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static const uint8_t TSLB_YLAST = 0x04; /* UYVY or VYUY - see com13 */
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static const uint8_t REG_COM11 = 0x3b; /* Control 11 */
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static const uint8_t COM11_NIGHT = 0x80; /* NIght mode enable */
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static const uint8_t COM11_NMFR = 0x60; /* Two bit NM frame rate */
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static const uint8_t COM11_HZAUTO = 0x10; /* Auto detect 50/60 Hz */
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static const uint8_t COM11_50HZ = 0x08; /* Manual 50Hz select */
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static const uint8_t COM11_EXP = 0x02;
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static const uint8_t REG_COM12 = 0x3c; /* Control 12 */
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static const uint8_t COM12_HREF = 0x80; /* HREF always */
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static const uint8_t REG_COM13 = 0x3d; /* Control 13 */
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static const uint8_t COM13_GAMMA = 0x80; /* Gamma enable */
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static const uint8_t COM13_UVSAT = 0x40; /* UV saturation auto adjustment */
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static const uint8_t COM13_UVSWAP = 0x01; /* V before U - w/TSLB */
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static const uint8_t REG_COM14 = 0x3e; /* Control 14 */
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static const uint8_t COM14_DCWEN = 0x10; /* DCW/PCLK-scale enable */
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static const uint8_t REG_EDGE = 0x3f; /* Edge enhancement factor */
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static const uint8_t REG_COM15 = 0x40; /* Control 15 */
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static const uint8_t COM15_R10F0 = 0x00; /* Data range 10 to F0 */
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static const uint8_t COM15_R01FE = 0x80; /* 01 to FE */
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static const uint8_t COM15_R00FF = 0xc0; /* 00 to FF */
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static const uint8_t COM15_RGB565 = 0x10; /* RGB565 output */
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static const uint8_t COM15_RGB555 = 0x30; /* RGB555 output */
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static const uint8_t REG_COM16 = 0x41; /* Control 16 */
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static const uint8_t COM16_AWBGAIN = 0x08; /* AWB gain enable */
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static const uint8_t REG_COM17 = 0x42; /* Control 17 */
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static const uint8_t COM17_AECWIN = 0xc0; /* AEC window - must match COM4 */
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static const uint8_t COM17_CBAR = 0x08; /* DSP Color bar */
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/*
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* This matrix defines how the colors are generated, must be
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* tweaked to adjust hue and saturation.
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*
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* Order: v-red, v-green, v-blue, u-red, u-green, u-blue
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* They are nine-bit signed quantities, with the sign bit
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* stored in0x58.Sign for v-red is bit 0, and up from there.
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*/
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static const uint8_t REG_CMATRIX_BASE = 0x4f;
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static const uint8_t CMATRIX_LEN = 6;
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static const uint8_t REG_CMATRIX_SIGN = 0x58;
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static const uint8_t REG_BRIGHT = 0x55; /* Brightness */
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static const uint8_t REG_CONTRAS = 0x56; /* Contrast control */
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static const uint8_t REG_GFIX = 0x69; /* Fix gain control */
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static const uint8_t REG_REG76 = 0x76; /* OV's name */
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static const uint8_t R76_BLKPCOR = 0x80; /* Black pixel correction enable */
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static const uint8_t R76_WHTPCOR = 0x40; /* White pixel correction enable */
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static const uint8_t REG_RGB444 = 0x8c; /* RGB 444 control */
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static const uint8_t R444_ENABLE = 0x02; /* Turn on RGB444, overrides 5x5 */
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static const uint8_t R444_RGBX = 0x01; /* Empty nibble at end */
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static const uint8_t REG_HAECC1 = 0x9f; /* Hist AEC/AGC control 1 */
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static const uint8_t REG_HAECC2 = 0xa0; /* Hist AEC/AGC control 2 */
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static const uint8_t REG_BD50MAX = 0xa5; /* 50hz banding step limit */
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static const uint8_t REG_HAECC3 = 0xa6; /* Hist AEC/AGC control 3 */
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static const uint8_t REG_HAECC4 = 0xa7; /* Hist AEC/AGC control 4 */
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static const uint8_t REG_HAECC5 = 0xa8; /* Hist AEC/AGC control 5 */
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static const uint8_t REG_HAECC6 = 0xa9; /* Hist AEC/AGC control 6 */
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static const uint8_t REG_HAECC7 = 0xaa; /* Hist AEC/AGC control 7 */
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static const uint8_t REG_BD60MAX = 0xab; /* 60hz banding step limit */
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static const uint8_t MTXS = 0x58; /* Matrix Coefficient Sign */
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static const uint8_t AWBC7 = 0x59; /* AWB Control 7 */
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static const uint8_t AWBC8 = 0x5a; /* AWB Control 8 */
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static const uint8_t AWBC9 = 0x5b; /* AWB Control 9 */
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static const uint8_t AWBC10 = 0x5c; /* AWB Control 10 */
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static const uint8_t AWBC11 = 0x5d; /* AWB Control 11 */
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static const uint8_t AWBC12 = 0x5e; /* AWB Control 12 */
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static const uint8_t REG_GFI = 0x69; /* Fix gain control */
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static const uint8_t GGAIN = 0x6a; /* G Channel AWB Gain */
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static const uint8_t DBLV = 0x6b;
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static const uint8_t AWBCTR3 = 0x6c; /* AWB Control 3 */
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static const uint8_t AWBCTR2 = 0x6d; /* AWB Control 2 */
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static const uint8_t AWBCTR1 = 0x6e; /* AWB Control 1 */
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static const uint8_t AWBCTR0 = 0x6f; /* AWB Control 0 */
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#endif
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