Finalized schematic
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parent
34691b370a
commit
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(kicad_pcb (version 20221018) (generator pcbnew)
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)
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(general
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(thickness 1.6)
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)
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(paper "A4")
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(layers
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(31 "B.Cu" signal)
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(32 "B.Adhes" user "B.Adhesive")
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(33 "F.Adhes" user "F.Adhesive")
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(34 "B.Paste" user)
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(37 "F.SilkS" user "F.Silkscreen")
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(38 "B.Mask" user)
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(39 "F.Mask" user)
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(40 "Dwgs.User" user "User.Drawings")
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(41 "Cmts.User" user "User.Comments")
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(42 "Eco1.User" user "User.Eco1")
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(43 "Eco2.User" user "User.Eco2")
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(44 "Edge.Cuts" user)
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(45 "Margin" user)
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(46 "B.CrtYd" user "B.Courtyard")
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(47 "F.CrtYd" user "F.Courtyard")
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(48 "B.Fab" user)
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(49 "F.Fab" user)
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(50 "User.1" user)
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(51 "User.2" user)
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(52 "User.3" user)
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(53 "User.4" user)
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(54 "User.5" user)
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(55 "User.6" user)
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(56 "User.7" user)
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(57 "User.8" user)
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(58 "User.9" user)
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)
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(setup
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(pad_to_mask_clearance 0)
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(pcbplotparams
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(layerselection 0x00010fc_ffffffff)
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(psnegative false)
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(outputformat 1)
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(outputdirectory "")
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)
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)
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(net 0 "")
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(net 1 "GND")
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(net 2 "3.3V_IN")
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(net 3 "+5V")
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(net 6 "Net-(R2-Pad1)")
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(net 7 "Net-(R3-Pad2)")
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(footprint "Package_TO_SOT_SMD:SOT-23-6" (layer "F.Cu")
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(tstamp ad1e0b6b-8b43-4bb1-b997-6e372e6366d6)
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(at 150.6275 73.345)
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(descr "SOT, 6 Pin (https://www.jedec.org/sites/default/files/docs/Mo-178c.PDF variant AB), generated with kicad-footprint-generator ipc_gullwing_generator.py")
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(tags "SOT TO_SOT_SMD")
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(property "Sheetfile" "ublox-lea-6h-breakout.kicad_sch")
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(property "Sheetname" "")
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(property "ki_description" "Very low capacitance ESD protection diode, 2 data-line, SOT-23-6")
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(rotate (xyz 0 0 0))
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)
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)
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(footprint "Package_TO_SOT_SMD:SOT-223-3_TabPin2" (layer "F.Cu")
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(at 152.9775 66.995)
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(descr "module CMS SOT223 4 pins")
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