200 lines
5.9 KiB
Rust
200 lines
5.9 KiB
Rust
use core::marker::PhantomData;
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use embedded_hal::blocking::i2c;
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const I2C_ADDR: u8 = 96;
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const CLK_ENABLE_CONTROL: u8 = 3;
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//const PLLX_SRC: u8 = 15;
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const PLL_RESET: u8 = 177;
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const XTAL_LOAD_CAP: u8 = 183;
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#[derive(PartialEq, Copy, Clone)]
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pub enum PLL {
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A,
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B,
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}
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const PLL_BASE_ADDR: [u8; 2] = [26, 34];
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impl PLL {
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fn base_address(&self) -> u8 {
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return PLL_BASE_ADDR[*self as usize];
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}
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}
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#[derive(Copy, Clone)]
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pub enum Multisynth {
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MS0,
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MS1,
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MS2,
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}
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const MS_BASE_ADDR: [u8; 3] = [42, 50, 58];
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const MS_CTRL_ADDR: [u8; 3] = [16, 17, 18];
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const CLK_PHOFF_ADDR: [u8; 3] = [165, 166, 167];
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impl Multisynth {
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fn base_address(&self) -> u8 {
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return MS_BASE_ADDR[*self as usize];
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}
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fn ctrl_address(&self) -> u8 {
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return MS_CTRL_ADDR[*self as usize];
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}
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fn phoff_address(&self) -> u8 {
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defmt::debug!("Adress: {}", CLK_PHOFF_ADDR[*self as usize]);
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return CLK_PHOFF_ADDR[*self as usize];
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}
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}
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pub struct PllParams {
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pub p1: u32,
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pub p2: u32,
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pub p3: u32,
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}
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pub struct Si5153<I2C> {
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// Marker that makes sure we always get the same I2C
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i2c: PhantomData<I2C>,
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pll_freqs: [u32; 2],
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outputs: u8,
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ms_srcs: [PLL; 3],
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}
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impl<I2C, E> Si5153<I2C>
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where
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I2C: i2c::Write<Error = E>,
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{
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pub fn new(_i2c: &I2C) -> Self {
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Si5153 {
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i2c: PhantomData,
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pll_freqs: [0, 0],
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outputs: 0,
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ms_srcs: [PLL::A, PLL::A, PLL::A],
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}
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}
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pub fn init(&mut self, i2c: &mut I2C, freq_xtal: u32, freq_a: u32, freq_b: u32) {
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self.pll_freqs[PLL::A as usize] = freq_a;
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self.pll_freqs[PLL::B as usize] = freq_b;
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self.outputs = 0xFF;
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs); // Disable all outputs
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self.write_byte_reg(i2c, XTAL_LOAD_CAP, 0xD2); //crystal load capacitor = 10pF
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for ms in [Multisynth::MS0, Multisynth::MS1, Multisynth::MS2].iter() {
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self.ms_srcs[*ms as usize] = PLL::A;
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self.write_byte_reg(i2c, ms.ctrl_address(), 0x0F); // MSi as Source, PLLA to MSi, 8 mA output
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self.write_byte_reg(i2c, ms.phoff_address(), 0); // Phase offset to 0.
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}
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for pll in [PLL::A, PLL::B].iter() {
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let fdiv = self.pll_freqs[*pll as usize] / freq_xtal;
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let rm = self.pll_freqs[*pll as usize] % freq_xtal;
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//TODO: Find better way to determine c and b
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let c = 0x0FFFFF;
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let a = fdiv;
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let b = ((rm as u64) * (c as u64) / (freq_xtal as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, pll.base_address(), ¶ms)
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}
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self.write_byte_reg(i2c, PLL_RESET, 0xA0); // Reset both PLLs
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}
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pub fn enable_ms_output(&mut self, i2c: &mut I2C, synth: Multisynth) {
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self.outputs &= !(1 << (synth as u8));
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs);
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}
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pub fn disable_ms_output(&mut self, i2c: &mut I2C, synth: Multisynth) {
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self.outputs |= 1 << (synth as u8);
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs);
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}
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pub fn set_ms_source(&mut self, i2c: &mut I2C, synth: Multisynth, pll: PLL) {
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let value: u8 = if pll == PLL::A {
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self.ms_srcs[synth as usize] = PLL::A;
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0x0F // MS as Source, PLLA to MS, 8 mA output
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} else {
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self.ms_srcs[synth as usize] = PLL::B;
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0x2F // MS as Source, PLLB to MS, 8 mA output
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};
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self.write_byte_reg(i2c, synth.ctrl_address(), value);
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}
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pub fn set_ms_freq(&mut self, i2c: &mut I2C, synth: Multisynth, freq: u32) {
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let pll = self.ms_srcs[synth as usize];
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let fdiv = self.pll_freqs[pll as usize] / freq;
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let rm = self.pll_freqs[pll as usize] % freq;
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//TODO: Find better way to determine c and b
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let c: u32 = 0x0FFFFF;
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let a: u32 = fdiv;
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let b: u32 = ((rm as u64) * (c as u64) / (freq as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, synth.base_address(), ¶ms)
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}
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pub fn set_ms_phase(&mut self, i2c: &mut I2C, synth: Multisynth, phase: u8) {
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self.write_byte_reg(i2c, synth.phoff_address(), phase);
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match self.ms_srcs[synth as usize] {
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PLL::A => {
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self.write_byte_reg(i2c, PLL_RESET, 1 << 5);
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}
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PLL::B => {
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self.write_byte_reg(i2c, PLL_RESET, 1 << 7);
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}
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}
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}
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pub fn pll_reset(&mut self, i2c: &mut I2C) {
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self.write_byte_reg(i2c, PLL_RESET, 0xA0);
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}
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fn write_byte_reg(&self, i2c: &mut I2C, reg_addr: u8, data: u8) {
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let res = i2c.write(I2C_ADDR, &[reg_addr, data]);
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if res.is_err() {
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panic!("i2c write failed. regAdder: {}", reg_addr)
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}
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}
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fn write_params(&self, i2c: &mut I2C, base: u8, params: &PllParams) {
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let data: [u8; 9] = [
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base,
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((params.p3 & 0x00FF00) >> 8) as u8,
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(params.p3 & 0x0000FF) as u8,
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((params.p1 & 0x030000) >> 16) as u8,
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((params.p1 & 0x00FF00) >> 8) as u8,
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(params.p1 & 0x0000FF) as u8,
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(((params.p3 & 0x0F0000) >> 12) | ((params.p2 & 0x0F0000) >> 16)) as u8,
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((params.p2 & 0x00FF00) >> 8) as u8,
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(params.p2 & 0x0000FF) as u8,
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];
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let res = i2c.write(I2C_ADDR, &data);
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if res.is_err() {
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panic!("i2c write failed. regAdder: {}", base)
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}
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}
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pub fn write_synth_params(&self, i2c: &mut I2C, synth: Multisynth, params: &PllParams) {
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self.write_params(i2c, synth.base_address(), params);
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}
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}
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