Initial Commit

.cargo/config

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+[target.thumbv7m-none-eabi]
+# uncomment this to make `cargo run` execute programs on QEMU
+# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

.gdbinit

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+target remote :3333
+monitor arm semihosting enable
+load
+tbreak main
+monitor reset halt
+continue
+
+#source .gdbdash

.gitignore

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+**/*.rs.bk
+.#*
+.gdb_history
+Cargo.lock
+target/

Cargo.toml

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+[package]
+authors = ["sebastian"]
+edition = "2018"
+readme = "README.md"
+name = "STM32F1Test"
+version = "0.1.0"
+
+[dependencies]
+cortex-m = "0.5.8"
+cortex-m-rt = "0.6.5"
+cortex-m-semihosting = "0.3.2"
+panic-halt = "0.2.0"
+
+[dependencies.stm32f1]
+version = "0.7.0"
+features = ["stm32f103"]
+
+# Uncomment for the panic example.
+# panic-itm = "0.4.0"
+
+# Uncomment for the allocator example.
+# alloc-cortex-m = "0.3.5"
+
+# Uncomment for the device example.
+# [dependencies.stm32f30x]
+# features = ["rt"]
+# version = "0.7.1"
+
+# this lets you use `cargo fix`!
+[[bin]]
+name = "STM32F1Test"
+test = false
+bench = false
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations

build.rs

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+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}

memory.x

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+MEMORY
+{
+  /* STM32f1*/
+  FLASH : ORIGIN = 0x08000000, LENGTH = 0x00020000
+  RAM : ORIGIN = 0x20000000, LENGTH = 0x00005000
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* You may want to use this variable to locate the call stack and static
+   variables in different memory regions. Below is shown the default value */
+/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on microcontrollers that store some configuration right
+   after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */
+
+/* Example of putting non-initialized variables into custom RAM locations. */
+/* This assumes you have defined a region RAM2 above, and in the Rust
+   sources added the attribute `#[link_section = ".ram2bss"]` to the data
+   you want to place there. */
+/* Note that the section will not be zero-initialized by the runtime! */
+/* SECTIONS {
+     .ram2bss (NOLOAD) : ALIGN(4) {
+       *(.ram2bss);
+       . = ALIGN(4);
+     } > RAM2
+   } INSERT AFTER .bss;
+*/

run.sh

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+#!/bin/bash
+cargo build || exit -1
+arm-none-eabi-gdb target/thumbv7m-none-eabi/debug/STM32F1Test

src/main.rs

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+#![no_std]
+#![no_main]
+
+// pick a panicking behavior
+extern crate panic_halt; // you can put a breakpoint on `rust_begin_unwind` to catch panics
+// extern crate panic_abort; // requires nightly
+// extern crate panic_itm; // logs messages over ITM; requires ITM support
+use cortex_m_semihosting::hprintln; // logs messages to the host; requires a debugger
+
+use cortex_m::asm;
+use cortex_m_rt::entry;
+use stm32f1::stm32f103;
+
+#[entry]
+fn main() -> ! {
+    hprintln!("Hello, world!").unwrap();
+
+    let peripherals = stm32f103::Peripherals::take().unwrap();
+
+    let gpioc = &peripherals.GPIOC;
+    let rcc = &peripherals.RCC;
+    let flash = &peripherals.FLASH;
+
+    flash.acr.write(|w| unsafe { w.latency().bits(1)});
+
+    rcc.cr.write(|w| w.hseon().set_bit());
+    while rcc.cr.read().hserdy().is_not_ready() {};
+
+    hprintln!("HSE Ready.").unwrap();
+
+    rcc.cfgr.write(|w| {
+        w.pllmul().mul12()
+        .pllsrc().hse_div_prediv()
+        .pllxtpre().div2()
+        .ppre2().div2()
+    });
+
+    rcc.cr.modify(|_, w| w.pllon().on());
+    while rcc.cr.read().pllrdy().is_not_ready() {};
+
+    rcc.cfgr.modify(|_, w| { w.sw().pll() });
+
+
+    hprintln!("PLL running.").unwrap();
+
+
+    // enable the GPIO clock for IO port C
+    rcc.apb2enr.write(|w| w.iopcen().set_bit());
+    gpioc.crh.write(|w| {
+        w.mode13().bits(3)
+        .cnf13().bits(0b00)
+    });
+
+    loop{
+        gpioc.bsrr.write(|w| w.bs13().set_bit());
+        cortex_m::asm::delay(500_000);
+        gpioc.brr.write(|w| w.br13().set_bit());
+        cortex_m::asm::delay(500_000);
+        //hprintln!("Blink").unwrap();
+    }
+}