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Added some notes to readme

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Sebastian 2023-09-10 22:17:41 +02:00
parent c9e8cb7195
commit 9b9924d815
1 changed files with 5 additions and 3 deletions
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Readme.md
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@ -9,7 +9,7 @@ RX Path
and we need the comparator match event to trigger the ADC.
- ADC conversions are triggered externally at each comparator match for Timer1 Channel1
- ADC runs ins Scan-mode, it samples PA2 first, then PA3
- DMA2 is set up to for device to memory, with memory increment,
- DMA2 Stream 0 is set up to for device to memory, with memory increment,
transfer complete interrupt and double buffering disabled.
- The HAL requires the DMA transfer instance to take ownership of both buffers,
for the double buffered mode, to swap to the second buffer immediately,
@ -26,7 +26,7 @@ RX Path
- The samples are scaled by 2**10 and turned into an array of 128 complex numbers.
- A FIR-filter for filtering out the sideband is applied to the array
- The resulting audio is stored in the output buffer
- DMA1 is set up to transfer the output buffer into CCR3 of Timer4
- DMA1 Stream 7 is set up to transfer the output buffer into CCR3 of Timer4
- Similar to the ADC two buffers are used alternating.
they are swapped out in the transfer complete interrupt.
- Timer4 is set up to output PWM on Channel3 on PB8
@ -57,4 +57,6 @@ TX Path
-TODO:
- Extracting the amplitude and dominant frequency
- Predistorted the amplitudes using a LUT, to compensate for non-linearities of the MOSFETs
- Setup DMA transfers for I2C and bias PWM
- Setup DMA transfers for I2C and bias PWM
- DMA1 - Stream 6 for I2C1 TX
- DMA1 - Stream 4 for TIM1 CH3