Added basic tuning via encoder
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parent
4878a1a771
commit
35ad5dcb9f
57
src/main.rs
57
src/main.rs
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@ -69,8 +69,8 @@ mod app {
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board_led: gpioc::PC13<Output<PushPull>>,
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rx_en: gpioa::PA7<Output<PushPull>>,
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//mic_in: gpio::Pin<'A', 4, Analog>,
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i_in: gpio::Pin<'A', 1, Analog>,
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q_in: gpio::Pin<'A', 0, Analog>,
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i_in: gpio::Pin<'A', 2, Analog>,
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q_in: gpio::Pin<'A', 3, Analog>,
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i_offset: f32,
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q_offset: f32,
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audio_pwm: AudioPwm,
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@ -93,6 +93,10 @@ mod app {
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disp: ST7735<Spi<SPI1>, gpio::Pin<'A', 12, Output>, gpio::Pin<'A', 11, Output>>,
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col_pos: u16,
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max_mag: f32,
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encoder: qei::Qei<TIM2>,
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last_encoder_pos: u32,
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carrier_freq: u32,
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}
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#[shared]
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@ -125,14 +129,12 @@ mod app {
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let board_led = gpioc.pc13.into_push_pull_output();
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/*
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let enc_a = gpioa.pa5.into_input();
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let enc_b = gpiob.pb3.into_input();
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let enc_a = gpioa.pa0.into_input();
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let enc_b = gpioa.pa1.into_input();
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let encoder = qei::Qei::new(cx.device.TIM2, (enc_a, enc_b));
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defmt::info!("Encoder Setup done");
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*/
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let scl = gpiob.pb6.into_alternate_open_drain();
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let sda = gpiob.pb7.into_alternate_open_drain();
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@ -152,8 +154,8 @@ mod app {
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let freq = 7_100_000;
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*/
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let phase = 36;
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let freq = 14_125_000;
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let phase = 100;
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let freq = 7_100_000;
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pll.init(&mut i2c, 25_000_000, freq * phase, freq * phase);
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pll.set_ms_source(&mut i2c, si5153::Multisynth::MS0, si5153::PLL::A);
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@ -201,8 +203,8 @@ mod app {
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defmt::info!("Display setup done");
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let i_in = gpioa.pa1.into_analog();
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let q_in = gpioa.pa0.into_analog();
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let i_in = gpioa.pa2.into_analog();
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let q_in = gpioa.pa3.into_analog();
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let adc_config = AdcConfig::default()
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.dma(Dma::Continuous)
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@ -307,11 +309,15 @@ mod app {
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disp,
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col_pos: 0,
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max_mag: 0.0,
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encoder,
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last_encoder_pos: 0,
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carrier_freq: 7_100_000,
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},
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)
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}
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#[task(priority = 0, local = [disp, col_pos, max_mag])]
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#[task(priority = 0, local = [disp, col_pos, max_mag, encoder, last_encoder_pos, carrier_freq, pll, i2c])]
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async fn update_display(cx: update_display::Context, col: [Complex<f32>; 128]) {
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for samp in col {
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let mag = (samp.re.pow(2) as f32 + samp.im.pow(2) as f32).sqrt() as f32;
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@ -341,6 +347,29 @@ mod app {
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*cx.local.max_mag *= 0.999;
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defmt::info!("Position is {}", cx.local.col_pos);
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let encoder_pos = cx.local.encoder.count();
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let diff = encoder_pos.wrapping_sub(*cx.local.last_encoder_pos) as i32;
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if diff != 0 {
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*cx.local.carrier_freq = (*cx.local.carrier_freq as i32 + diff * 100 / 4) as u32;
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cx.local
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.pll
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.set_pll_freq(cx.local.i2c, si5153::PLL::A, *cx.local.carrier_freq * 100);
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cx.local.pll.set_ms_freq(
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cx.local.i2c,
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si5153::Multisynth::MS0,
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*cx.local.carrier_freq,
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);
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cx.local.pll.set_ms_freq(
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cx.local.i2c,
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si5153::Multisynth::MS1,
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*cx.local.carrier_freq,
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);
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}
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defmt::info!("Carrier freq is {}", cx.local.carrier_freq);
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*cx.local.last_encoder_pos = encoder_pos;
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}
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#[task(binds = DMA2_STREAM0, local = [adc_transfer, iq_buffer, board_led, i_offset, q_offset, usb_filter, audio_max_duty], shared = [audio_buffer])]
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@ -365,7 +394,7 @@ mod app {
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let i_sample = (i_raw as f32) - *cx.local.i_offset;
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let q_sample = (q_raw as f32) - *cx.local.q_offset;
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samples[idx] = Complex::new(q_sample as f32 / 4096.0, i_sample as f32 / 4096.0);
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samples[idx] = Complex::new(q_sample as f32 / 4096.0, i_sample as f32 / 4096.0) * 5.0;
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}
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let mut fft_input = [Complex::<f32>::default(); 128];
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@ -376,8 +405,8 @@ mod app {
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cx.shared.audio_buffer.lock(|buffer| {
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let audio_buffer = buffer.take().unwrap();
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for idx in 0..samples.len() {
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//let filtered = usb_filter.compute(samples[idx]);
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let filtered = usb_filter.compute(Complex::new(samples[idx].im, samples[idx].re));
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let filtered = usb_filter.compute(samples[idx]);
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//let filtered = usb_filter.compute(Complex::new(samples[idx].im, samples[idx].re));
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fft_input[idx] = samples[idx];
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audio_buffer[idx] = ((filtered.re * (audio_max_duty as f32)) * 3.0f32) as u16;
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@ -57,6 +57,7 @@ pub struct PllParams {
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pub struct Si5153<I2C> {
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// Marker that makes sure we always get the same I2C
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i2c: PhantomData<I2C>,
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freq_xtal: u32,
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pll_freqs: [u32; 2],
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outputs: u8,
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ms_srcs: [PLL; 3],
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@ -69,6 +70,7 @@ where
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pub fn new(_i2c: &I2C) -> Self {
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Si5153 {
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i2c: PhantomData,
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freq_xtal: 0,
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pll_freqs: [0, 0],
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outputs: 0,
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ms_srcs: [PLL::A, PLL::A, PLL::A],
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@ -76,6 +78,8 @@ where
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}
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pub fn init(&mut self, i2c: &mut I2C, freq_xtal: u32, freq_a: u32, freq_b: u32) {
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self.freq_xtal = freq_xtal;
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self.pll_freqs[PLL::A as usize] = freq_a;
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self.pll_freqs[PLL::B as usize] = freq_b;
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@ -83,34 +87,38 @@ where
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs); // Disable all outputs
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self.write_byte_reg(i2c, XTAL_LOAD_CAP, 0xD2); //crystal load capacitor = 10pF
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self.set_pll_freq(i2c, PLL::A, freq_a);
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self.set_pll_freq(i2c, PLL::B, freq_b);
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for ms in [Multisynth::MS0, Multisynth::MS1, Multisynth::MS2].iter() {
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self.ms_srcs[*ms as usize] = PLL::A;
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self.write_byte_reg(i2c, ms.ctrl_address(), 0x0F); // MSi as Source, PLLA to MSi, 8 mA output
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self.write_byte_reg(i2c, ms.phoff_address(), 0); // Phase offset to 0.
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}
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for pll in [PLL::A, PLL::B].iter() {
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let fdiv = self.pll_freqs[*pll as usize] / freq_xtal;
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let rm = self.pll_freqs[*pll as usize] % freq_xtal;
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let gcd = num::integer::gcd(rm, freq_xtal);
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let c = if gcd < 0x0FFFFF { gcd } else { 0x0FFFFF };
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let a = fdiv;
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let b = ((rm as u64) * (c as u64) / (freq_xtal as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, pll.base_address(), ¶ms)
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}
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self.write_byte_reg(i2c, PLL_RESET, 0xA0); // Reset both PLLs
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}
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pub fn set_pll_freq(&mut self, i2c: &mut I2C, pll: PLL, freq: u32) {
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let fdiv = freq / self.freq_xtal;
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let rm = freq % self.freq_xtal;
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let gcd = num::integer::gcd(rm, self.freq_xtal);
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let c = if gcd < 0x0FFFFF { gcd } else { 0x0FFFFF };
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let a = fdiv;
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let b = ((rm as u64) * (c as u64) / (self.freq_xtal as u64)) as u32;
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let params = PllParams {
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p1: 128 * a + (128 * b / c) - 512,
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p2: 128 * b - c * (128 * b / c),
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p3: c,
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};
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self.write_params(i2c, pll.base_address(), ¶ms);
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self.pll_freqs[pll as usize] = freq;
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}
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pub fn enable_ms_output(&mut self, i2c: &mut I2C, synth: Multisynth) {
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self.outputs &= !(1 << (synth as u8));
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self.write_byte_reg(i2c, CLK_ENABLE_CONTROL, self.outputs);
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